The present invention relates to a semiconductor integrated circuit device and a manufacturing method therefor, and, more specifically, to a semiconductor integrated circuit device having an SOI (silicon on insulator) structure and a manufacturing method of the device.
In the following description, an n-channel MOSFET (metal-oxide semiconductor field-effect transistor) is referred to as an nMOS, a p-channel MOSFET as a pMOS, and a complementary MOSFET, a combination of these MOSFET's, as a CMOS.
Similarly, an n-channel MIS (metal-insulator semiconductor) FET is referred to as a nMIS, a p-channel MISFET as a pMIS, and a complementary MISFET, a combination of these MISFET's, as a CMIS.
The SOI technique is one that forms a specified semiconductor integrated circuit device (hereinafter referred to simply as a device) on a semiconductor thin film layer formed on an insulating layer, and has the following advantages, for example:
(1) Because complete device isolation is possible, the parasitic capacitance between interconnects and substrate and the diffusion layer capacitance can be reduced, improving the operation speed of the semiconductor integrated circuit device;
(2) Because the active parasitic devices such as parasitic MOS transistors and parasitic bipolar transistors can be prevented from being formed, it is possible to prevent latch-up; and
(3) Resistance against .alpha. ray software error, a problem encountered in semiconductor memory devices, can be improved.
Some descriptions on the SOI technique may be found, for example, in Japanese Patent Laid-Open No. 294076/1990. A CMOS gate array using the SOI technique is described, for example, in a publication "A High-Speed 0.6 .mu.m 16 k CMOS Gate Array on a Thin SIMOX Film" (IEEE Trans. on Electron Devices, published in January 1993, Vol. 40, No. 1, pp179-186).
This literature deals with a case where an nMOS is deposited on a semiconductor thin film layer formed on an insulating layer and discloses a technique to introduce a high concentration of p-type impurity into a channel region to set the threshold voltage to a specified value.
Setting the impurity concentration in a channel region high, however, reduces the mobility of carriers, which in turn lowers the transfer conductance of nMOS or the junction pressure resistance between drain region and channel region.
A technique to improve the situation mentioned above is introduced, for instance, in "Device/Circuit Simulation of Double-Gate SOI-MOSFET" (published Jan. 21, 1993, Denshi Joho Tsushin Gakkai Gijutsu Kenkyu Hokoku (Electronic Information Communication Society Meeting's Technical Report), Vol. 192, No. 424, SDM 92-137-149, pp27-32). This report describes a technology to control a threshold voltage of MOSFETs with the impurity concentration lowered in the channel region.
A method of fabricating a double-gate SOI-MOSFET is explained, for example, in "Analysis of p+ Polysilicon Double-Gate Thin-Film SOI MOSFETs" (Tech. Dig. 1991, pp683-686, IEDM (International Electron Device Meeting)). The technique introduced in this literature is shown in FIG. 43. On a semiconductor substrate 60 is formed an insulation layer 61, on which a semiconductor layer 62 is deposited. On the semiconductor layer 62 is formed an nMOS 63, which consists of a pair of semiconductor regions 64, 64 formed in the semiconductor layer 62, a gate insulation film 65 overlying the semiconductor layer 62, and a gate electrode 66 of p-type polysilicon formed over the gate insulation film 65.
This fabrication technique also forms in the insulation layer 61, another gate electrode 67 of p-type polysilicon having a size sufficient to substantially overlap the pair of semiconductor regions 64, 64 to permit the threshold voltage of the nMOS 63 to be set at a desired value with the impurity concentration lowered in the channel region of the nMOS 63. The gate electrode 67 is electrically connected to the gate electrode 66 of the nMOS 63. The method of fabrication introduced in this literature is explained by referring to FIGS. 44(a) through 44(d).
Double-gate SOI MOSFETs were fabricated as shown in FIG. 44(a). A thick field oxide is formed by conventional selective oxidation. The oxide acts as a stopper when polishing the silicon layer. A polysilicon back gate (p.sup.+ type) is then formed by conventional methods, followed by a SiO.sub.2 layer being deposited by CVD (chemical vapor deposition) and then planarized by polishing.
As shown in FIG. 44(b), a BPSG (boron-doped phospho-silicate glass) film is deposited on the base wafer. Two wafers are bonded through CVD SiO.sub.2 and BPSG by pulse-field-assisted bonding at 900.degree. C. in a 0.1 PaN.sub.2 atmosphere.
The silicon active layer is thinned by selective polishing. The thickness of the Si active layer is determined by a field oxide stopper.
The front gate (p.sup.+ type poly Si gate) is formed by conventional methods.
The method shown in FIGS. 44(a) to 44(d) requires a heat treatment at elevated temperatures at around 900.degree. C. in a wafer bonding process in which two wafers are bonded together.